Hardware Security Research Internship

About Internship

Assistant Professor from Thapar Institute of Engineering and Technology, Patiala (TIET Patiala), is accepting interns interested in the field of Computer Science Engineering, in the research area of Computer Architecture & Graphics.

This research internship investigates the security frontier of emerging memory hierarchies, specifically Hybrid SRAM-STTRAM architectures. As traditional memory scaling hits physical limits, non-volatile solutions like STT-MRAM offer energy benefits but introduce unique Side-Channel Attack (SCA) vectors due to their distinct latency and power profiles. Interns will work to identify how these hardware characteristics leak information and will architect low-overhead defense mechanisms to build the next generation of resilient, high-performance cache systems. Roles and Responsibilities : 1. Design and implement sophisticated side-channel models (e.g., timing or occupancy-based) tailored to exploit the unique write-endurance and latency of STTRAM. 2. Design and code defense mechanisms within the cache controller to mitigate information leakage while maintaining energy efficiency. 3. Modify and extend industry-standard simulators like ChampSim or Gem5 to model hybrid cache controllers and complex migration policies. 4. Use tools like McPAT to analyze power-area-timing trade-offs and quantify the security-performance overhead. 5. Analyze simulation traces to calculate security metrics and validate the effectiveness of proposed mitigations against known attacks like Prime+Probe. Learning Outcomes: 1. Gain deep, internal knowledge of memory hierarchies, cache replacement, and the physics of emerging non-volatile memory. 2. Develop a specialized "security mindset," learning to identify and patch physical-layer vulnerabilities that software cannot see.